Threaded prefetching: An adaptive instruction prefetch mechanism

We propose and analyze an adaptive instruction prefetch scheme, called threaded prefetching, that makes use of history information to guide the prefetching. The scheme is based on the observation that control ow paths are likely to repeat themselves. In the proposed scheme, we associate with each instruction block a number of threads that indicate the instruction blocks that have been brought into the cache by the current block. These threads later trigger the prefetching of the indicated instruction blocks once the instruction block containing them are re-accessed by the processor. These pointers, in eeect, encode the causal relationship between an instruction block and the instruction blocks that have been brought into the cache by the block. The results from trace-driven simulations using SPEC benchmarks show that the proposed scheme improves the prefetch accuracy by more than 100 % on average for 32 Kbyte cache. They also show that the scheme signiicantly (80 % on average for 32Kbyte cache) improves the CPI (Clocks Per Instruction) due to instruction references over the sequential prefetching.